In recent years, as an interconnect material of a semiconductor device, copper (Cu) with low resistivity has been used as one of means for reducing interconnect delay in order to increase an operation frequency of the device. In a Cu interconnect process, a diffusion prevention film (barrier metal) and an electroplated base conductive film (Cu seed) are sequentially formed in a trench (interconnect groove) which is provided in an insulating film, by using a sputtering method, and a Cu interconnect is metalized therein so as to be formed by using an electroplating method. Metallization characteristics of the Cu interconnect are defined depending on a coating shape of the seed layer, metallization performance of electrolytic plating, or the like, but there is a limitation in performance of metallization into a minute shape. Thus, a perfect metallization without defects is not easy in an ultra-narrow trench, and, as a result, void defects may be generated. Particularly, in a case where void defects are generated inside the interconnect, the defects cause disconnection, an increase in interconnect resistance, and a reduction in resistance to electro-migration. Therefore, poor metallization of the Cu interconnect is critically problematic in relation to interconnect reliability, and further semiconductor device performance, and thus there is a demand for a technique of detecting voids in the Cu interconnect in line. In addition, in order to detect voids caused by the process in line and to feedback a result thereof to a process condition, it is necessary to quickly detect the voids in a nondestructive manner.
Since voids are present inside an interconnect, the voids cannot be detected by an optical inspection apparatus of a dark field and bright field type used for typical semiconductor device inspection. Generally, a planarization step (CMP) is performed, and then voids are detected by using an SEM. In order to detect voids present inside an interconnect by using the SEM, electron beams with high energy can penetrate into a specimen, and thus it is necessary to irradiate the specimen with electron beams with a high accelerating voltage of 5 kV or higher. However, contrasts of crystal grains (grains) appear along with the voids under the high accelerating voltage, and thus there is a case where the grains and the voids are hardly differentiated from each other only on the basis of an SEM image. In order to detect the voids, an FIB+SEM/TEM method in which cross-section processing of an interconnect portion using a focused ion beam (FIB) apparatus is combined with void detection using a TEM or an SEM should be applied. In this FIB+SEM/TEM method, a cross-section of interconnect created with FIB is observed by using the SEM or TEM so that voids can be reliably specified, but the method has a problem in that a specimen is partially or completely destructed, and thus much time is required to prepare and observe the specimen. From the above facts, a void detection method is desirable which can be applied to an in-line inspection and allows voids to be easily detected at a high speed in a nondestructive manner.
As the related art for detecting voids, there is a CMP method in which wafer surface polishing using chemical-mechanical polishing (CMP) is combined with void detection using an optical type exterior inspection apparatus. In addition, there is a probe test method or the like in which electric resistance of an interconnect portion is measured, and Cu voids are detected on the basis of the fact that the electric resistance increases if voids are present.
PTL 1 discloses a technique in which the same portion is observed by variously changing electron beam incidence directions in a TEM so that crystal defects are observed, as a technique of detecting crystal defects corresponding to grains, or defects of a plug and a via interconnect by using the TEM.